This invention relates in general to semiconductor devices and to a method for fabricating those devices, and more particularly to bipolar transistors having improved switching performance and whose fabrication is concomitant with existing MOS process methods.
Vertical bipolar switching transistors are commonly used in integrated circuits for data storage and logic flow control. In high speed devices, both the electrical resistance and the parasitic capacitance in the transistor must be minimized so that the transistor can switch on and off rapidly. In addition, bipolar transistors used in advanced VLSI BiCMOS devices must meet further performance criteria and design constraints which are related to the signal transmission requirements of the associated MOS transistors. For example, high speed bipolar switching transistors used in BiCMOS circuits must be designed to have minimal signal propagation delay. The most direct method for boosting the signal transmission rate and increasing the switching speed is to reduce the electrical resistance and the capacitance within the transistor.
The electrical resistance can be reduced by fabricating the bipolar transistor in a thin epitaxial layer grown on a single crystal semiconductor substrate. The thin epitaxial layer reduces the current path length between the emitter and the collector; however, the electrical resistance in the collector itself represents a major component of the overall electrical resistance in the bipolar transistor. A low resistance collector contact structure is usually fabricated by performing a heavy implant into a selected portion of the epitaxial layer, then diffusing the dopant atoms through the epitaxial layer to a heavily doped buried layer located in the single crystal substrate. Collector resistance has a dominant effect on signal propagation delay of a bipolar transistor under heavy capacitive loading. For BiCMOS applications, NPN transistors have collector current densities on the order of 400 to 800 microamps per square micrometer. The formation of a low resistance collector presents a problem unique to BiCMOS devices in that the dopant diffusion process used to form the collector in a conventional bipolar transistor causes unwanted lateral diffusion of dopants in the associated MOS transistors found in a BiCMOS device. One solution to the lateral diffusion problem is to form a collector plug by etching a trench through the epitaxial layer to expose a portion of the buried collector, then filling the trench with doped polysilicon. The collector plug forms a low resistance contact to the buried collector while avoiding the problem of subjecting the MOS devices to a long thermal cycle. To further reduce the collector resistance, the current path between the base-collector junction and the collector electrode contact at the surface of the epitaxial layer should be a short as possible. Again, one possibility is to make the epitaxial layer very thin thereby reducing the length of the collector plug. However, the minimum epitaxial layer thickness is set by the collector-emitter breakdown voltage and the collector capacitance. For example, for a minimum collector-emitter breakdown voltage of 7 V an epitaxial layer thickness of about 1.25 micrometers is required. Furthermore, continued thinning of the epitaxial layer is undesirable because the out-diffusion of dopants from the heavily doped buried layer into the thin epitaxial layer increases the collector capacitance. As the epitaxial layer becomes very thin, the out-diffusion of buried layer dopants raises the dopant concentration in the epitaxial layer to unacceptably high levels and parasitic capacitance slows the switching speed.
In view of the limitation to a further reduction in the thickness of the epitaxial layer, one method for partially decreasing the current path length in the transistor is to reduce the lateral separation distance between the emitter, the base. This approach has the added benefit of permitting more transistors to be placed in a smaller surface area on a chip thereby increasing the packing density and enabling higher integration levels in VLSI circuits. The lateral separation between the emitter electrode and the base electrode is reduced by providing an opening in the base electrode overlying the active region. The emitter electrode is then formed over a portion of the base electrode and makes an emitter contact to the active region through the opening in the base electrode. An intermediate isolation layer is used to insure that the emitter electrode remains electrically isolated from the base electrode. Transistor designs of this type have been described by, for example, H. Nakashiba et al., IEEE Trans. Elect. Dev. ED-27 (8), p. 1390, 1980 and R. A. Chapman et al. IEEE IEDM, p 756, 1988. This structure provides a narrow emitter width and a low base resistance, however, the collector separation distance is not considered in this design.
While some benefit is obtained from a reduction in the emitter-base lateral separation distance, the structures of the prior art do not solve the most critical problem of total electrical path length and in particular the problem of excessive separation of the collector contact structure from the emitter-base junction. Therefore, it would be desirable to fabricate a bipolar transistor, in a manner compatible with an MOS process sequence, which maintains the advantage of a heavily doped collector plug while minimizing the lateral separation of the collector, base and emitter electrodes.